A serializer/deserializer (SerDes) is commonly used in devices for high speed communications to convert data between serial and parallel interfaces in each transmit/receive direction. As in most types of communication receivers, SerDes devices employ amplification of received signals prior to equalization (e.g., in a linear equalizer (LEQ) and subsequent processing (e.g., Multiplexers (MUX) and decision feedback qualization (DFE)). Amplification is usually accomplished using a variable gain amplifier (VGA). Unfortunately, the VGA and other circuits implemented in a semiconductor technology/geometry are subject to performance variation due to process, voltage and temperature (process (P), voltage (V) (e.g., supply VDD) and temperature (T), collectively known as (PVT)) variations during operation. P, V, and T corners represent the extremes of these parameter variations, with the performance at fast (FFF) and slow (SSS) corners (along with T and V corners) often employed to characterize performance of a device under PVT variations.
As technology shrinks in geometry, the PVT variation is amplified. The PVT variation manifests itself as variations in circuit gain
      gm    =                  δ        ⁢                                  ⁢                  I          D                            δ        ⁢                                  ⁢                  V          GS                      ;which can be represented in various forms,
      gm    =          μ      ⁢                          ⁢              C        ox            ⁢              w        L            ⁢              (                              V            GS                    -                      V            th                          )              ,            or      ⁢                          ⁢      gm        =                  2        ⁢                  I          D                                      V          GS                -                  V          th                      ,          ⁢            where      ⁢                          ⁢              I        D              =                  1        2            ⁢              μ        n            ⁢              C        ox            ⁢              W        L            ⁢                                    (                                          V                GS                            -                              V                th                                      )                    2                .            The variations in W, L, μ, Vgs, Vth over PVT corners create variations in gm.
In a SerDes receive (Rx) data path, variations in VGA, LEQ, MUX, and DFE data path gains create an accumulated composite gain variation. In an exemplary SerDes receiver the gain variation approaches 20 dB. With such wide data path gain variation, the system bit error rate (BER) performance objectives are generally not met reliably. In case of a high gain corner (usually slow process, high VDD, low T corner) the signal is highly compressed and loses adaptation information, which in turn results in sub-optimal receiver operation. In case of a low gain corner (usually fast process, low VDD, high T corner) the signal cannot be amplified, and remain attenuated even at the highest VGA setting. As a result, the device cannot meet operating BER performance for low launch (low transmitter signal power) applications. An approach for a solution is compensation for PVT variation. One approach overdrives transistors with excessive current increase transistor gain gm. Increasing system power budget might help the fast gain corner reach sub-optimal operating performance at the expense of degrading the slow gain corner even more. In general, present SerDes device designs are optimized for PVT compensation using open loop PVT compensation circuits. In existing approaches, the SerDes device is designed for the worst case scenario that results in dissipating more power and consumes more area than might be required for typical application in the absence of PVT variations.
An eye pattern, also known as an eye diagram (the “eye), represents a digital data signal from a receiver that is repetitively sampled and applied to the vertical input (axis), while the horizontal input (axis) represents time as a function of the data rate. The eye diagram allows for evaluation of the combined effects of channel noise and inter-symbol interference on the performance of a baseband pulse-transmission system, and the eye is the synchronized superposition of all possible realizations of the signal of interest viewed within a particular signaling interval.
When sampling the input signal, the data latch employed to make a decision for the data or symbol value is usually placed within the center of the eye. When a DFE is present, the first tap value H0 for the DFE is usually placed at an error location (usually at the top or bottom of the eye rails vertically from the data decision latch) and is adapted as part of the adaptive equalization process. In the context of evaluating PVT variation, similar H0 variation, or “spread” occurs as variations in process corners over all V and T corners. At the FFF process corner, the H0 level is relatively small, magnitude tends to be lower, and indicates poor gain in the FFF corner that dominates over V and T corners. On the other hand, at the SSS process corner, the H0 level is relatively large, magnitude tends to be higher, and indicates higher gain in SSS corner. In a conventional SerDes receiver, adaptation of DFE target level is within its set upper and lower limit. Anytime the target level is exceeded, the VGA is adaptively operated by varying its voltage regulator to pull in the DFE H0 value within the set upper and lower limit.